1. Field of the Invention
The present invention generally relates to semiconductor devices provided with circuitry for testing a memory, and particularly relates to a semiconductor device provided with a memory BIST circuit for testing a memory and to a voltage control method using a memory BIST circuit.
2. Description of the Related Art
In semiconductor devices such as processors provided with one or more built-in memories, scan chains are generally used to test the operation of each memory through a limited number of external terminals. The SCAN chain is a chain that allows data to propagate as the data is serially input from an exterior. Flip-flops connected in series are provided along the SCAN chain. Data is serially input into the flip-flops from a tester situated outside the semiconductor device, thereby setting an input test pattern for each memory. Results of a test of each memory's operation are output to an exterior, and the tester is used to check whether the tested operation was satisfactory.
In a test method using such a scan chain, data is set according to the clock rate of the external tester. In a current state of technology, however, the clock rate of the external tester is generally far lower than the actual operating frequency used inside the semiconductor device. Because of this, a lengthy time is required for testing memory operations, and it is not possible to detect a malfunction that may occur only when an actual operating frequency is used in the semiconductor device. Such malfunction may include a malfunction that is caused by the failure affecting a delay time, e.g., a contact failure.
There is a test method that provides a memory BIST (Built-In-Self-Test) circuit around each memory and uses this memory BIST circuit to generate a test pattern and to check test results (for example, Japanese Patent Application Publication No. 2000-163993, Japanese Patent Application Publication No. 2003-346498, Japanese Patent Application Publication No. 2000-200874). Even where a memory BIST circuit is used, the memory BIST circuit is connected to a SCAN chain, and data for controlling the memory BIST circuit is supplied through the SCAN chain from outside the device. Namely, the control of the memory BIST circuit is carried out according to the clock rate of the external tester, and, also, the operation of the memory BIST circuit is performed at this clock rate. Consequently, the test of memory operations requires a lengthy time, and fails to detect a malfunction that may come to the surface only when an actual operating frequency is used.